In recent years, digital household electric appliances including battery-driven types such as cell phones, digital cameras, portable audio players and the like, and stationary types such as digital TV sets, digital video disk players, digital hard disk recorders and the like have become compact, thin and light-weight, and semiconductor integrated circuit devices such as digital LSI (Large Scale Integration) and the like have been used widely.
Semiconductor microfabrication technologies to manufacture digital LSI have been developed more year after year, and for example by making the gate width and oxide file thickness and the like of a CMOS (Complementary Metal Oxide Semiconductor) circuit thinner, it has been possible to manufacture the digital LSI itself thinner and smaller. The compact and thin and light-weight structure of the digital LSI is regarded as the value of semiconductor.
Further, in order to make the gate width and the oxide film thickness thin, it is necessary to make the power source voltage to be applied to the digital LSI low at the same time. As a result, in order to secure the same processing capacity or more than that of digital LSI produced by the one generation prior microfabrication technology, that is, to produce digital LSI that can be driven at the same operation frequency or more, from the relation between withstand voltage and the oxide film thickness, it is necessary to make the power source voltage low, and at the same time to make the threshold value voltage lower than that of the digital LSI.
However, when the threshold voltage is made low, whether the digital LSI is driven or not, that is, whether the CMOS circuit is switched or not, the increase of leakage current which has the characteristic that as long as the power source voltage is applied, current leaks and energy is consumed unintentionally becomes prominent.
In the years before 2000, the switching current having the characteristic that energy is consumed when the CMOS circuit is actually driven occupied the large portion of the entire power consumption. However, it is forecasted that after the year 2000, along with the progress of microfabrication technologies, the ratio of energy consumption by leakage current will become dominant exponentially.
Therefore, the trend goes to the phase not to realize a digital LSI of the same processing capacity or more than that of the digital LSI by making the power source voltage low, and making the operation frequency high, but to realize a digital LSI by not setting the power source voltage as low as possible, that is, by preventing the decline of the threshold value voltage, and driving similar plural processing mechanisms in parallel.
For example, it is not to realize a high speed processor, but to realize a mixed loading chip of plural processors and ASIC (Application Specific Integrated Circuit) that can operate in parallel.
The above consideration helps prevention of the exponential increase of the leakage current, and easily realizes the compact and thin and light-weight structure of digital LSI that is regarded as the value of semiconductors, by microfabrication technologies.
Further, when the compact and thin and light-weight structure of digital LSI is realized, products are differentiated with the same chip area as that of the digital LSI, and by adding further processing functions, therefore, loading more plural processors and ASIC that can perform parallel processing than the mixed loading chip, that is, integration is performed consequently.
However, in integration, the number of transistors showing the CMOS circuit scale per unit chip area increases, the LSI gets to have a large load capacity, and the power consumption by switching current increases. It is forecasted that around the year 2010, the number of processors and ASIC loaded per one chip will be several ten to one hundred, and the power source voltage will become saturated while become low, on the contrary, the consumption current as the sum of the switching current and the leakage current will be increasing in proportion to the number of processors and ASIC loaded per one chip.
There are occurring two main problems to be solved in the low voltage and large current age in the future, arising from microfabrication and integration of digital LSI. One is the heat design power problem to occur with the digital LSI itself becoming a heat generation source, and the other is the electromagnetic noise countermeasure problem to occur with the digital LSI itself becoming an electromagnetic noise generation source.
The thermal design power problem is the problem in designing the package of digital LSI by use of heat calculation equation. Whether the digital LSI is driving or not, consumed power is converted into heat in accordance to the amount of current consumed, and increases the temperature of digital LSI itself.
In the chip temperature, there exists a temperature range to guarantee proper operation, and when the temperature range is exceeded, digital LSI sees malfunction, and in the worst case, the CMOS circuit is broken and operations cannot be made. In the personal computer and the like, a cooling fan is arranged at the vicinity of LSI, and thereby chip temperature increase is prevented.
However, the cooling fan causes noise, therefore, it is not desired to package the cooling fan to digital household electric appliances. Further, there is a case where a route to dissipate heat such as a heat sink or the like is arranged in package, thereby the chip temperature increase is prevented.
In the future, when microfabrication and integration are applied to digital LSI, the consumption current will increase and the chip temperature will increase, and there is a fear that the chip temperature may exceed the range of the temperature to guarantee proper operation.
Further, the electromagnetic noise countermeasure issue is the problem concerning the system design of entire semiconductor integrated circuit device from digital LSI to a board on which the digital LSI is loaded. The electromagnetic noise is the total value of the value of DC component voltage of consumption current occurring by resistance components of entire power source wiring circuit including digital LSI and battery loaded on the board, and the value of AC component voltage change of consumption current occurring by inductance components formed in the entire power source wiring circuit.
The value of the DC component voltage corresponds to the product IR of the resistance value R of the entire power source wiring circuit and the value I of consumption current. Meanwhile, the value of the change in AC component voltage change corresponds to the product L×(dI/dt) of the inductance value L of the entire power source wiring circuit and the change ratio dI/dt of consumption current per unit time.
In the electromagnetic noise, there exists an allowable operation voltage margin, and the operation voltage margin is the voltage equivalent to approximately 5% of the power source voltage.
However, along with fine configuration, the power source voltage is saturated but low, and the operation voltage margin also becomes small. In general, it is necessary to make the electromagnetic noise limited in the range of the operation voltage margin.
If the power source noise exceeds the operation voltage margin, some phenomena occur like the power source voltage and the grounding potential those are normally constant fluctuate largely, and the Power Integrity is deteriorated.
And at the same time, the Signal Integrity among circuits becomes deteriorated, LSI sees malfunction, and in the worst case, by occurrence of unnecessary radiation, that is, unnecessary electromagnetic wave, EMI (Electromagnetic Interface) exceeds allowable values, leading to an environmental issue.
In the future, when microfabrication and integration are applied to digital LSI, the consumption current and the time change ratio of the consumption current will easily increase, and there is a fear that the electromagnetic noise may exceed the range of the operation voltage margin that will become smaller.
Accordingly, in order to manufacture digital LSI while maintaining its compact and thin and light-weight structure and multi functions by fine configuration and integration, it is necessary to provide some feature and design to digital LSI so as to make the chip temperature where consumption current is going to increase in future becomes the main factor within the range of the operation guarantee temperature, and make the power source noise which comes to the main factor limited in the range of the operation voltage margin, power budget value at which the power supply is available under the maximum power of the semiconductor integrated circuit device is preset, and application specifications can be satisfied within the range of the power budget value.
In general, as technologies to make the consumption current small, there are two technologies. One is power gating technology wherein power shutout to shut out power source voltage and action block shutout to shut out operation clock and the like are arranged to plural processors and ASIC loaded on digital LSI, and the other is power control technology wherein power source voltage or operation frequency is controlled for the processors and ASIC.
The present inventors had examinations on a power consumption control device according to the prior art disclosed in Japanese Patent Laid-Open No. H8-152945 (Patent Document 1, hereinafter), with the digital household electric appliances as objectives before the present application. The Patent Document 1 is a patent concerning a power consumption control device wherein the power control technology is employed and application specifications are satisfied within the power budget value. Further, in the Patent Document 1, the use of the power gating technology is included. Before extracting problems, the Patent Document 1 is explained.
FIG. 21 is a structural diagram of a power consumption control device described in FIG. 4 of the Patent Document 1, and FIG. 22 is a structural diagram of a power consumption control device described in FIG. 2 of the Patent Document 1.
Function blocks 111 request for necessary power according to the present load condition. An information collection unit 104 adds and collects required power from the respective function blocks. A supply power distribution determination unit 102, when the total of added and collected power is within supplyable power value, instructs a power distribution unit 105 and outputs power requirement to the respective function blocks, and when the total of power exceeds the supplyable power value, it determines a power distribution method according to a predetermined method, and instructs the power distribution unit 105 and distributes and outputs supplyable power to the respective function blocks according to the power distribution method.
In the power consumption control technology by a power consumption control device of such a structure, there are the following problems to be solved.
First, as the first problem, for example when the function block 111 is a processor that can flexibly change processing contents, different from ASIC where the power value can be fixed, the required power is different per processing content, that is, per task, therefore, the number of combinations of power distribution 203 is large and they become complicated, therefore it is difficult to package a power distribution candidate table unit 202, and it poses a problem.
Further, a power consumption control device 401 has the power distribution candidate table unit 202, selection unit 204 and distribution unit 206 thereon, even when desired plural function blocks 111 work it sets the power distribution unit 105 with appropriate power distribution 203, thereby it can perform the power supply control within the power budget value.
However, as the second problem, for example, when the function block to which the power distribution unit 105 supplies low power source voltage and low operation frequency, that is, supplies low power in the course of process and satisfies a specified process to complete it, since the priority and the contents of the power distribution method are not clear, there is a fear that it cannot supply high power to the power distribution unit 105 and high speed processing cannot ever be recovered.
Further, when the total required power exceeds the power budget value in the course of process, for example, in the case where the total required power is made low to a certain function block 111 according to a priority by use of the power gating technology, since the process of the function block 111 is stopped by the power consumption control unit 401, if the power consumption control unit 401 lets the function block 111 be uncontrolled, operation cannot be made later, and there occurs a fear that the dead line of application specifications cannot be satisfied.
Accordingly, it is necessary to set time for the function block 111 that is in stop state according to the priority and release the stop state to supply power and the like.
The third problem is that the power consumption of the power consumption control unit 401 is added to the total required power.
When the digital LSI is realized by one digital LSI, it is necessary to make the total required power including the power consumption control unit 401 within the power budget value.
Further, the fourth problem is to limit the maximum power value of the digital LSI within the allowable power of power source IC.
When the power consumption control unit fails rapid sampling of large total required power by simultaneous driving of many function blocks, that is, when timing of comparison with the power budget value is lost, the allowable power of power source IC is exceeded, and sufficient power cannot be supplied to the respective function blocks, and the process is broken and nonconformity occurs.
Accordingly, it is necessary to estimate power margin within allowable power precisely and limit the maximum power.
The fifth problem is to judge whether the set of function blocks is in idle state or not.
In the case where the digital LSI is realized by one semiconductor integrated circuit device, it is ideal to arrange a power source voltage distribution unit per function block, however, in order to prevent the chip area of digital LSI from becoming large, the power source voltage distribution unit is often allotted and packaged to a set of relative function blocks.
Therefore, if it is known that all the function blocks belonging to the set are in idle state, shutdown of power source voltage can be made collectively for the function blocks belonging to the set, and low power consumption can be realized.
The sixth problem is that even when plural function blocks 111 are loaded, it is necessary to set power in other function blocks than the power consumption control unit.
When the function block 111 is regarded as a processor or a controller, normally, it is possible to change the power source voltage value and settings of operation frequency of the power distribution unit 105 from software that operates the function block, for example, before the function block completes a specified process and gets in idle state, by setting of the software, the function block itself can get in stop state, and therefore low power consumption can be realized.
However, in the power consumption control unit 401 in Patent Document 1, power setting can be made only by the power consumption control unit, therefore, it is necessary to arrange a mechanism to set power from the function block.